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PRELIMINARY
CY7C1062DV33
16-Mbit (512K X 32) Static RAM
Features
* High speed -- tAA = 10 ns * Low active power -- ICC = 150 mA @ 10 ns * Low CMOS standby power -- ISB2 = 25 mA * Operating voltages of 3.3 0.3V * 2.0V data retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE1, CE2, and CE3 features * Available in Pb-free 119-ball plastic ball grid array (PBGA) package
Functional Description
The CY7C1062DV33 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bits. Writing to the device is accomplished by enabling the chip (CE1, CE2 and CE3 LOW) and forcing the Write Enable (WE) input LOW. If Byte Enable A (BA) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte Enable B (BB) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). Likewise, BC and BD correspond with the I/O pins I/O16 to I/O23 and I/O24 to I/O31, respectively. Reading from the device is accomplished by enabling the chip (CE1, CE2, and CE3 LOW) while forcing the Output Enable (OE) LOW and Write Enable (WE) HIGH. If the first Byte Enable (BA) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte Enable B (BB) is LOW, then data from memory will appear on I/O8 to I/O15. Similarly, Bc and BD correspond to the third and fourth bytes. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O31) are placed in a high-impedance state when the device is deselected (CE1, CE2or CE3 HIGH), the outputs are disabled (OE HIGH), the byte selects are disabled (BA-D HIGH), or during a write operation (CE1, CE2, and CE3 LOW, and WE LOW). The CY7C1062DV33 is available in 119-ball plastic ball grid array (PBGA) package.
Logic Block Diagram
INPUT BUFFERS
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
ROW DECODER
512K x 32 ARRAY
OUTPUT BUFFERS
SENSE AMPS
WE CE1 CE2 CE3 OE BA BB BC BD I/O0-I/O31
COLUMN DECODER
Cypress Semiconductor Corporation Document #: 38-05477 Rev.*C
A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 4, 2006
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CONTROL LOGIC
PRELIMINARY
Selection Guide
-10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 10 150 25
CY7C1062DV33
Unit ns mA mA
Pin Configuration[1]
119-ball PBGA
(Top View)
1 A B C D E F G H J K L M N P R T U
Note: 1. NC pins are not connected on the die
2
A A Bc VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A
3
A A CE2 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS Bd A A
4
A CE1 NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC WE OE
5
A A CE3 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS Bb A A
6
A A Ba VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A
7
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 NC I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31
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PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................-65C to +150C Ambient Temperature with Power Applied .............................................-55C to +125C Supply Voltage on VCC Relative to GND[2] ..... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ................................... -0.5V to VCC + 0.5V
CY7C1062DV33
DC Input Voltage[2] ................................-0.5V to VCC + 0.5V Current into Outputs (LOW) .........................................20 mA Static Discharge Voltage ............................................>2001V (per MIL-STD-883, Method 3015) Latch-up Current......................................................>200 mA
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 3.3V 0.3V
DC Electrical Characteristics Over the Operating Range
-10 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current --TTL Inputs Automatic CE Power-down Current --CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC IOUT = 0 mA CMOS levels Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1
[7]
Min. 2.4
Max. 0.4 VCC + 0.3 0.8 +1 +1 150 30 25
Unit V V V V A A mA mA mA
Capacitance[3]
Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 10 Unit pF pF
Thermal Resistance[3]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board All - Packages TBD TBD Unit C/W C/W
AC Test Loads and Waveforms[4]
50 OUTPUT Z0 = 50 (a) *Capacitive Load consists of all
components of the test environment
VTH = 1.5V 30 pF*
All input pulses 3.0V GND Rise time > 1V/ns (c) 90% 10% 90% 10% Fall time: > 1V/ns
3.3V OUTPUT 5 pF* *Including jig and scope
R1 317
R2 351
(b)
Notes: 2. VIL (min.) = -2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. 4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100s (tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
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PRELIMINARY
AC Switching Characteristics Over the Operating Range[5]
-10 Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Cycle[10, 11] Write Cycle Time CE active LOW LOW to Write Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z[8] WE LOW to High-Z
[8]
CY7C1062DV33
Description VCC (typical) to the first access[6] Read Cycle Time Address to Data Valid Data Hold from Address Change CE active LOW to Data Valid[7] OE LOW to Data Valid OE LOW to Low-Z
[8] [8]
Min. 100 10
Max.
Unit s ns
10 3 10 5 1 5 3 5 0 10 5 1 5 10 End[7] 7 7 0 0 7 5.5 0 3 5 7
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High-Z
CE active LOW to Low-Z[7, 8] CE deselect HIGH to CE active LOW to CE deselect HIGH to Byte Enable to Byte Disable to High-Z[7, 8] Power-down[7, 9] Power-up[7, 9]
Byte Enable to Data Valid Low-Z[8] High-Z[8]
Byte Enable to End of Write
Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading as shown in (a) of AC Test Loads, unless specified otherwise. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 and CE2 and CE3 LOW. When deselect HIGH, CE indicates the CE1 or CE2 or CE3 HIGH 8. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 9. These parameters are guaranteed by design and are not tested. 10. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 LOW, CE3 LOW and WE LOW. The chip enables must be active and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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PRELIMINARY
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR[3] tR[12] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 2V , CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 0 Conditions
CY7C1062DV33
Min. 2 25 Typ. Max. Unit V mA ns ns
tRC
Data Retention Waveform
DATA RETENTION MODE VCC 3V tCDR CE VDR > 2V 3V tR
Switching Waveforms
Read Cycle No. 1[13,14]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 15, 15]
ADDRESS CE tRC
tACE OE tDOE BA, BB, BC, BD tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% ISB IICC CC tHZOE
HIGH IMPEDANCE
DATA OUT
Notes: 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s 13. Device is continuously selected. OE, CE, BA, BB, BC, BD = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW.
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PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[15, 16, 17]
CY7C1062DV33
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE tBW BA, BB, BC , BD tSD DATAI/O tHD
tHA
Write Cycle No. 2 (BA, BB, BC, BD Controlled)[15, 16, 17]
tWC ADDRESS
tSA BA, BB, BC , BD tAW
tBW
tHA tPWE
WE tSCE CE tSD DATAI/O
Notes: 16. Data I/O is high-impedance if OE or BA, BB, BC, BD = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
tHD
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PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
CY7C1062DV33
tWC ADDRESS
CE
tSCE
tAW tSA tPWE
tHA
WE tBW BA, BB, BC, BD tHZWE DATA I/O tLZWE tSD tHD
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PRELIMINARY
Truth Table
CE1 CE2 CE3 H X X L L L L L L L L L L L X H X L L L L L L L L L L L X X H L L L L L L L L L L L OE X X X L L L L L X X X X X H WE X X X H H H H H L L L L L H BA X X X L L H H H L L H H H X BB X X X L H L H H L H L H H X Bc X X X L H H L H L H H L H X BD X X X L H H H L L H H H L X
CY7C1062DV33
Mode Power
I/O0-I/O7 I/O8-I/O15 I/O16-I/O23 I/O24-I/O31 High-Z High-Z High-Z Data Out Data Out High-Z High-Z High-Z Data In Data In High-Z High-Z High-Z High-Z High-Z High-Z High-Z Data Out High-Z Data Out High-Z High-Z Data In High-Z Data In High-Z High-Z High-Z High-Z High-Z High-Z Data Out High-Z High-Z Data Out High-Z Data In High-Z High-Z Data In High-Z High-Z High-Z High-Z High-Z Data Out High-Z High-Z High-Z Data Out Data In High-Z High-Z High-Z Data In High-Z
Power Down (ISB) Power Down (ISB) Power Down (ISB) Read All Bits (ICC) Read Byte A (ICC) Bits Only Read Byte B (ICC) Bits Only Read Byte C (ICC) Bits Only Read Byte D (ICC) Bits Only Write All Bits (ICC) Write Byte A (ICC) Bits Only Write Byte B (ICC) Bits Only Write Byte C (ICC) Bits Only Write Byte D (ICC) Bits Only Selected, Outputs Disabled Selected, Outputs Disabled (ICC)
L
L
L
X
X
H
H
H
H
High-Z
High-Z
High-Z
High-Z
(ICC)
Ordering Information
Speed (ns) 10 Ordering Code CY7C1062DV33-10BGXI Package Diagram 51-85115 Package Type 119-ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-free) Operating Range Industrial
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PRELIMINARY
Package Diagram
119-ball PBGA (14 x 22 x 2.4 mm) (51-85115)
CY7C1062DV33
51-85115-*B
All product and company names mentioned in this document may be the trademarks of their respective holders
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
Document History
Document Title: CY7C1062DV33 16-Mbit (512K X 32) Static RAM Document Number: 38-05477 REV. ** *A *B ECN NO. Issue Date 201560 233748 469420 See ECN See ECN See ECN Orig. of Change SWI RKF NXR Description of Change Advance Data sheet for C9 IPP
CY7C1062DV33
1.AC, DC parameters are modified as per EROS (Spec # 01-2165) 2.Pb-free offering in the `ordering information' Converted from Advance Information to Preliminary Removed -8 and -12 speed bins from product offering Removed Commercial operating Range Changed J7 ball of PBGA from DNU to NC in the pinout diagram Included the Maximum ratings for Static Discharge Voltage and Latch Up Current on page #3 Changed ICC(Max) from 220 mA to 150 mA Changed ISB1(Max) from 70 mA to 30 mA Changed ISB2(Max) from 40 mA to 25 mA Specified the Overshoot spec in footnote # 1 Changed tSD from 5.5 ns to 5 ns Added Data Retention Characteristics table and waveform on page # 5. Updated the 48-pin FBGA package Updated the Ordering Information Table Added note# 1 for NC pins Updated Test Condition for ICC in DC Electrical Characteristics table Added note for tACE, tLZCE, tHZCE, tPU, tPD, tSCE in AC Switching Characteristics Table on page# 4
*C
499604
See ECN
NXR
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